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NXP Semiconductors
PCA9530
2-bit I 2 C-bus LED dimmer
5. Pinning information
5.1 Pinning
A0
1
8
V DD
A0
1
8
V DD
LED0
LED1
V SS
2
3
4
PCA9530D
7
6
5
SDA
SCL
RESET
LED0
LED1
V SS
2
3
4
PCA9530DP
7
6
5
SDA
SCL
RESET
002aae496
002aae497
Fig 2.
Pin con?guration for SO8
Fig 3.
Pin con?guration for TSSOP8
(MSOP8)
5.2 Pin description
Table 2.
Pin description
Symbol
A0
LED0
LED1
V SS
RESET
SCL
SDA
V DD
Pin
1
2
3
4
5
6
7
8
Description
address input 0
LED driver 0
LED driver 1
supply ground
active LOW reset input
serial clock line
serial data line
supply voltage
6. Functional description
Refer to Figure 1 “Block diagram” .
6.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9530 is shown in Figure 4 . To conserve power, no
internal pull-up resistor is incorporated on the hardware selectable address pin and it must
be pulled HIGH or LOW.
slave address
1
1
0
0
0
0
A0 R/W
fixed
hardware
selectable
002aae499
PCA9530_3
Fig 4.
Slave address
? NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 26 February 2009
3 of 24
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